AMD 3D V-Cache Stack, vertical stacking for Zen 3+ CPUs

It has been at Computex 2021 the place AMD has stunned everybody with the brand new announcement in its vary of gaming CPUs for the tip of 2021 to compete in opposition to Intel’s Alder Lake-S. The novelty is just one, however it should skyrocket the efficiency of the processors and has given us yet another clue concerning the design of Zen 3. It will. 3D V-Cache Stack with TSMC on the helm.

AMD 3D V-Cache Stack, TSMC’s X3D implementation for Zen 3

The firm already warned in 2018 that it was engaged on a brand new layered improvement mannequin within the purest Intel Foveros fashion known as X3D, and since then we’ve solely seen brush strokes. At least till AMD has pulled the canvas and proven nothing lower than a prototype of Ryzen 9 5900X with know-how of vertical stacking for SRAM as an L3 cache.

The knowledge is partly concrete, but in addition partly concise and we are going to absolutely discuss extra about this know-how sooner or later. But the novelty is the novelty and the information is beginning to come out and it is actually fascinating. On the one hand, AMD confirms that this know-how 3D V-Cache Stack It will attain present CPUs with Zen Three structure, however to be extra particular, it should attain Ryzen CPUs solely, at the least for now and ready for Zen 4.

This excludes the brand new Milan server processors and the Threadripper, so AMD seeks to face out within the sector the place there may be extra competitors immediately: in gaming or maistream.

The CPUs aren’t in manufacturing but, however are anticipated to return shortly with TSMC to be launched on the earliest in late 2021 or early 2022, curiously across the Alder Lake-S presentation and launch dates. At the identical time this reveals that AMD will take at the least 6 extra months to launch Zen Four as such.

On the opposite hand, it’s curious how these statements don’t affirm or deny if we are going to see them solely on the desktop or this know-how may also be prolonged to laptops with monolithic die, and by default, it isn’t specified whether or not they are going to attain the brand new APUs.

The Physical Limits of 3D V-Cache Technology Revealed

What we additionally know for positive is that in stated die a SRAM stack can be interposed vertically as a cache with an actual measurement of 64 MB within the type of L3, which added to the 32 MB that the Ryzen have already got with two dies will do a complete of 96 MB of L3 cache.

But we go additional, since AMD specifies 1 stack of 3D V-cache for every chiplet, that’s, within the Ryzen 9 we’ve a lot of 192MB complete L3. Most stunning of all, AMD itself claims that V-Cache stacks can go as much as Eight stacks, additionally known as 8-hi.

Logically, sooner or later we might be speaking about nothing lower than 512MB of L3 plus the cache itself that the CCDs have, an actual outrage that may increase the efficiency of any processor to limits that proper now we will not even think about.

The present drawback and for which no extra stacks are carried out is the peak. AMD has needed to cut back the general peak of the CCD and SRAM to keep up the heights that the unique Ryzen had for it IO die.

Die measurement, warmth and unknowns

It just isn’t the primary design as such in 3D that we see, however it’s the first that’s proven in a CPU that’s at present in the marketplace as an evolution of it. The doubts are being generated and as such, the speculations proceed their course. But within the meantime we’ve affirmation of the dimensions of AMD’s 3D bundle: 6 x 6 mm, that’s, an space of 36 mm2 This is what 3D V-Cache know-how will occupy within the new Ryzen.

As the SRAM is on high of the CCDs, AMD has had so as to add two silicon brackets to the perimeters of it, welded to the dies, which equalizes the peak of the meeting and likewise permits the warmth output of the cores to be optimum and it hardly has a detrimental impact.

This is feasible as a result of not like the added Cache, the 2 spring silicons don’t embrace TSV, whereas logically the primary does. This hybrid method in accordance with AMD itself permits the density of the interconnections to be elevated 200 instances and the general effectivity of the interconnects is improved as much as Three instances, so we will think about the variety of pipes which were created for that objective.

The enhancements are very consultant as seen within the demo of the Ryzen 5900X with 3D V-Cache: + 12% on Gears V, a median improve of the 15% in gaming and a throughput of as much as 2 TB / s of complete inner bandwidth within the processor and its cache, which implies that for the primary time in historical past the L3 would outperform the L1.

It stays to be seen whether or not AMD will certainly introduce these 64MB of L3 in all fashions or will solely embrace 32 MB in people who carry a single CCD, the place on the identical time the query arises as as to if these new processors already baptized as Zen 3+ will arrive at the next value.

If certainly this 3D V-Cache manages to enhance gaming efficiency by 15% on common, can Intel counteract this impact with Alder Lake-S when it’s a completely new structure and it appears that evidently it isn’t targeted on the gamer as such?

For now we all know that from the outset we can have these Ryzen, and that the following processors to incorporate 3D V-Cache would be the new Milan-X, which ought to arrive in 2022 to additional increase its efficiency.