This is why AMD is going to overtake Intel in gaming CPUs this year

What each AMD and TSMC are doing is very spectacular, maybe not on the stage of Intel with Foveros (for now) however what is sure is that though technologically they don’t seem to be up to the duty for now, in efficiency they’re going to place themselves as leaders. (besides shock with Alder Lake-S).

AMD Zen three 3D Caché, a efficiency bounce of 15% in gaming

The numbers slipped by Lisa Su give this determine as a median end result, however now we all know the curiosities of the whys. And is that including yet another vertical chip as an elevated cache won’t be, as was speculated, a stage four cache, or in different phrases, it won’t be the standard Victim Caché technically talking.

Everything is a lot less complicated from principle, however from apply the numbers are overwhelming and we clarify ourselves.

What AMD achieves with this vertical cache is that Windows and CCDs see the added chip as “clear”, that is, there is no bodily change to the software program or {hardware} in their mode of operation between cores and the IOD.

What you will note is yet another L3 cache block, which will probably be manufactured at 7nm by TSMC and can measure a whopping 6 x 6mm (36mm2) related instantly to the CCD caches through TSV. And right here comes the magic, as a result of in the case of the 5950X that was proven on the time with this know-how we communicate of a minimum of 192 MB of L3 in complete for the 64 current of the unique mannequin that we are able to presently purchase.

TSV figures dizzying, on the top of Intel


Each CPU could have greater than 2 TB / s of bandwidth thanks to this new cache and its TSV connections, which we now know are made by Bumps in what is referred to as as “Face Down”, Each TSV is related from the FEOL of every CCD to the Bonding Surface via Nails coppermade. They are in direct contact with the BEOL of this new cache, which permits the change of knowledge from substrates and caches.

To give us an thought of ​​the complexity of all this vertical stacking, it is calculated that for each four MB L3 partition that has a CCD there is 3000 TSV with a measurement that features between the 6.1 μm and 17.three μm thick.


To sq. the circle, extra stratospheric information are given, since in the SMU they’re calculated 56 TSV and 14 extra in the so-called take a look at space.

What do we have now in complete in the brand new 5950X? Well, a whopping 24070 TSVs to join each substrates, the place as we have now stated earlier than the world of ​​the brand new AMD 3D Cache is solely 36 mm2. Undoubtedly staggering numbers and that may enable AMD to beat Intel down, no less than momentarily.